Alif Semiconductor /AE722F80F55D5LS_CM55_HP_View /ETH /ETH_DMA_INTERRUPT_STATUS

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Interpret as ETH_DMA_INTERRUPT_STATUS

MACIS=Val_0x0, MTLIS=Val_0x0, DC0IS=Val_0x0

Description

DMA, MTL, and MAC Interrupt Status Register

Fields

DC0IS	DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0. To reset this bit to 0x0, the software must read the corresponding register in DMA Channel 0 to get the exact cause of the interrupt and clear its source. 0 (Val_0x0): DMA channel 0 interrupt status not detected 1 (Val_0x1): DMA channel 0 interrupt status detected
MTLIS	MTL Interrupt Status This bit indicates an interrupt event in the MTL. To reset this bit to 0x0, the software must read the corresponding register in the MTL to get the exact cause of the interrupt and clear its source. 0 (Val_0x0): MTL interrupt status not detected 1 (Val_0x1): MTL interrupt status detected
MACIS	MAC Interrupt Status This bit indicates an interrupt event in the MAC. To reset this bit to 0x0, the software must read the corresponding register in the MAC to get the exact cause of the interrupt and clear its source. 0 (Val_0x0): MAC interrupt status not detected 1 (Val_0x1): MAC interrupt status detected

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